@MASTERSTHESIS\{IMM2003-01830,
    author       = "K. Larsen",
    title        = "SoC system level integration",
    year         = "2003",
    keywords     = "SystemC, core-centric protocol, communication wrapper, digital signal processing, {DSP,} mini-cores, Open Core Protocol, {OCP,} {WISHBONE,} system-on-chip, SoC, system level integration, on-chip interconnect",
    school       = "Informatics and Mathematical Modelling, Technical University of Denmark, {DTU}",
    address      = "Richard Petersens Plads, Building 321, {DK-}2800 Kgs. Lyngby",
    type         = "",
    url          = "http://www2.compute.dtu.dk/pubdb/pubs/1830-full.html",
    abstract     = "The trend within SoC (System-on-Chip) design is a decreased time-to-market. One of the measures to comply with this is to reuse previously designed cores or to purchase {IP} (Intellectual Property) cores, thus decreasing design time. In order easily to employ such cores in a design, the cores must be constructed independently of specific communication formats, i.e.\verb+~+the cores must utilize general purpose communication interfaces suitable for a variety of designs.

To adapt the cores to the communication format of the SoC on-chip interconnect, an external module must be constructed converting between the communication format of the core and of the interconnect. Such an architecture is often referred to as communication wrapping. In this thesis general purpose interfaces are defined and communication wrappers are constructed for both cores and interconnect, allowing easy substitution of both. The communication format employed between wrapped cores and wrapped interconnect is the {OCP} (Open Core Protocol). {OCP} is what often is referred to as a core-centric protocol, indicating that it is designed with emphasis on the needs of the core. Furthermore constructed are methods capable of logging information about the data traffic of the SoC. The information is stored in files allowing post processing of the data.

The communication format of {OCP} wrapped cores and interconnect including logging of data traffic is introduced in an existing SoC. This SoC is a heterogeneous processor architecture developed specifically for flexible low power digital signal processing. The system referred to as the mini-core system currently contains two core types, both processors dedicated at a specific digital signal processing task. 

The entire mini-core system has been reimplemented as a behavioral model to simplify the design, in order to ease experimenting with and testing the system. All implementation has been performed in SystemC.

The behavioral mini-core system has been tested with the original communication format and with the {OCP} wrapping architecture. The test showed unaltered functionality. The advantages and disadvantages of the implemented structure are assessed and discussed."
}