A microprocessor model as a bus-traffic generator for SoC performance analysis | Syed Faisal Ali
| | Abstract | In this thesis, we have designed a core model of microprocessor that can be used for performance evaluation of any communication architecture. In its outer form, this model is an entity in VHDL. To do performance evaluation for any communication architecture, several instances of this entity can be made depending upon the requirement and are then connected to the memory according to the configuration of that communication architecture. These models then generate traffic on the bus to communicate with the memory. At the end, these models generate report about their performance. Most important in that report is the effective CPI (Cycles per Instruction) under the given communication architecture.
The main feature of this model is that it performs simulation very fast as compared to the behavior models of microprocessors. For e.g., it can simulate 1 million instructions in nearly 1-2 minutes on SUN machines. Whereas, the complex models of microprocessors require 2-3 hours or even more for the same number of instructions. Moreover, it doesn t require any software to run i.e. to perform simulation it does not require that some software should be loaded into the memory. It can perform simulation without any original software to generate some performance statistics.
Although in its outer form it is a core model of a microprocessor (an entity in VHDL), it can also be termed as a tool to analyze performance of a system. Because it can only be used for performance estimation purposes and is not a hardware design. | | Type | Master's thesis [Academic thesis] | | Year | 2002 | | Publisher | Informatics and Mathematical Modelling, Technical University of Denmark, DTU | | Address | Richard Petersens Plads, Building 321, DK-2800 Kgs. Lyngby | | Series | IMM-THESIS-2002-70 | | Electronic version(s) | [pdf] [ps] | | BibTeX data | [bibtex] | | IMM Group(s) | Computer Science & Engineering |
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