DTU 02211: Advanced Computer Architecture

This course is an advanced course for Master's and PhD students, and it is lectured in English. The course is offered during the spring term by the DTU Compute department at the Technical University of Denmark.

Aims of the course

Computer architecture, the art and science of designing hardware, is an exciting and fast changing research and development field. In this course we intend to transfer this excitement to the students.

Students will learn the organization and design of contemporary processor architectures. The foundations such as instruction set, pipelining, and memory hierarchies are reviewed. We will cover advanced concepts such as instruction-level parallelism, out-of-order execution, and chip-multiprocessing. As the current trend in computer architecture is towards chip-multiprocessing, the architecture of shared memory multiprocessors and chip level interconnect (network-on-chip) will be a central focus of the course.

Most processors (99+%) are used in embedded systems, and many of those embedded systems are real-time systems. Therefore, processors need to be designed in a way that worst-case execution time analysis is feasible. We will cover current research in the field of time-predictable architectures.

Tentative List of Topics


The course is intended for students enrolled in the master program in computer systems engineering, and could also be interesting for students in the electrical engineering master program. Depending on your background the prerequisites are as follows:

Schedule, Format, Place

The course is lectured Tuesday afternoons 13:00 - 17:00.
First part is usually lectures and second part for project work.

The courese is lectured in building 325, room 009.

The course will start 2017 31 January.

Recommended Textbook

Computer Architecture: A Quantitative Approach
Fifth Edition

John L. Hennessy and David A. Patterson

Morgan Kaufmann, 2012

ISBN-13: 978-0-12-383872-8

The book is available from Polyteknisk Boghandel in Building 101A.


Martin Schoeberl
Jens Sparsø


Students will work in groups of two or three on a hardware or software project. A hardware project can be work within the T-CREST platform or building a pipelined processor from scratch. Software projects will explore embedded chip-multiprocessor programming and programming models. Besides a working solution, students will prepare a conference-style paper on their project. The project and paper will be presented in class. Exceptional projects shall lead to publications in computer architecture conferences.

We will provide a list of project suggestions. Students are also welcome to propose their own project that fits with their research interest.

More details on the projects are available in the Wikiversity page.


Following are the main categories for the project:
  1. Projects within the T-CREST platform
  2. Roll your own microprocessor
  3. Network-on-Chip
  4. Software for CMP
Please refer to that Wiki page for latest information.

Look up the assignments there and start a page for your project at the SS2017 page and read about the assignments.

Assignments and Points

50% of the grade are from the lab project. The lab project itself includes a few exercises to get you started, but the main part is the project.

Warm-up Lab

In the first lab we will start with a FPGA Hello World example on the FPGA board.

Notes on Tools

For the T-CREST exercise and FPGA development in general we provide a Ubuntu VM with all tools installed at Patmos page.


In the lab we need only free software:
  1. FPGA synthesis: Altera Quartus or Xilinx ISE
  2. ModelSim for VHDL simulation, also available for free from Altera
ModelSim is automatically added to the PATH, for the Altera tools you need to do this manually.
The driver for the USB-Blaster can be found in the Altera installation under quartus/drivers/usb-blaster.


The FPGA tools are not available under OS X. Therefore, use a VM with Linux (use the Ubuntu VM from the Patmos web site). Best option is VMware, which provides a free VMPlayer.

Lecture Plan

Tentative plan, that will change.

Week 1: Introduction & Instruction Set Review & Chisel: Overview

Reading: H & P: Appendix A and RISC-V ISA document
Lab: Instruction set comparison

Week 2: Pipeline Review & Chisel: Basic Operations

Reading: H & P: Appendix C
Lab: FPGA Hello World with Chisel

Week 3: Cache Review & Chisel: Scala and Chisel Background

Reading: H & P: Appendix B and Chapter 2
Lab: UART in Chisel

Week 4: Time-Predictable Computer Architecture & Chisel: Customized Circuit Generation

Reading: Paper on time-predictable architectures
Lab: Patmos exercise

Week 5: Instruction Level Parallelism

Reading: H & P: Chapter 3 Section 3.1 till 3.3
Lab: Start of your project

Week 6: Fundamental Concepts of NoC

Reading: A Survey of Research and Practices of Network-on-Chip
Lab: Project work

Week 7: Real-Time NoC

Reading: Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation
Lab: Message passing NoC exercise

Week 8: IO and Interconnect

Reading: Patmos handbook: Section 3.6 and 3.7
Lab: Project work

Week 9: Instruction-Level Parallelism II

Reading: H & P: Chapter 3
Lab: Project work

Week 10: Thread-Level Parallelism

Reading: H & P: Chapter 5
Lab: Project work

Week 11: Chip-Multiprocessing

Reading: H & P: Chapter 5
Lab: Project work

Week 12: Real-Time Caches, Project Work

Reading: Papers
Lab: Project work

Week 13: Wrap-up, Project Presentation

Reading: none
Lab: Project presentation and demonstration

Pensum List

Book chapters from Computer Architecture: A Quantitative Approach Fifth Edition