This page is not used in Spring 2023. See DTU Learn instead. Use this page only for ideas on hardware design projects.

DTU 02211: Advanced Computer Architecture

This course is an advanced course for Master's and PhD students, and it is lectured in English. The course is offered during the spring term by the DTU Compute department at the Technical University of Denmark.

Aims of the course

Computer architecture, the art and science of designing hardware, is an exciting and fast changing research and development field. In this course we intend to transfer this excitement to the students.

Students will learn the organization and design of contemporary processor architectures. The foundations such as instruction set, pipelining, and memory hierarchies are reviewed. We will cover advanced concepts such as instruction-level parallelism, out-of-order execution, and chip-multiprocessing. As the current trend in computer architecture is towards chip-multiprocessing, the architecture of shared memory multiprocessors and chip level interconnect (network-on-chip) will be a central focus of the course.

Most processors (99+%) are used in embedded systems, and many of those embedded systems are real-time systems. Therefore, processors need to be designed in a way that worst-case execution time analysis is feasible. We will cover current research in the field of time-predictable architectures.

Tentative List of Topics

Review of pipelining and caches
Instruction-level parallelism
Chip-multiprocessing
Network-on-chip
Time-predictable computer architecture

Prerequisites

The course is intended for students enrolled in the master program in computer systems engineering, and could also be interesting for students in the electrical engineering master program. Depending on your background the prerequisites are as follows:

02155 Computer Architecture and Engineering (strongly recommended) and
02203 Design of Digital Systems or
02139 Digital Electronics 2

Schedule, Format, Place

The course is lectured Tuesday 13:00 - 17:00.
First part is usually lectures and second part for project work.

The course is lectured in building 358 room 915.

Instructor

Martin Schoeberl

Project

Students will work in groups of two or three on a hardware or software project. A hardware project can be work within the T-CREST platform or building a pipelined processor from scratch. Software projects will explore embedded chip-multiprocessor programming and programming models. Besides a working solution, students will prepare a conference-style paper on their project. The project and paper will be presented in class. Exceptional projects shall lead to publications in computer architecture conferences.

We will provide a list of project suggestions. Students are also welcome to propose their own project that fits with their research interest.

More details on the projects are available in the Wikiversity page.

Topics

Following are the main categories for the project:

Projects within the T-CREST platform
Roll your own microprocessor
Network-on-Chip
Software for CMP

Find here a list of projects.

Please refer to that Wiki page for latest information.

Look up the assignments there and start a page for your project at the SS2022 page and read about the assignments.

Assignments and Points

50% of the grade are from the lab project. The lab project itself includes a few exercises to get you started, but the main part is the project.

Warm-up Lab

In the first lab we will start with a FPGA Hello World example on the FPGA board.

Notes on Tools

For the T-CREST exercise and FPGA development in general we provide a Ubuntu VM with all tools installed at Patmos page.

Fur TU Vienna, the TI lab has prepared a VM shared for several courses.

Software

In the lab we need only free software:

FPGA synthesis: Altera Quartus or Xilinx Vivado

The driver for the USB-Blaster can be found in the Altera installation under quartus/drivers/usb-blaster.

Mac

The FPGA tools are not available under OS X. Therefore, use a VM with Linux (use the Ubuntu VM from the Patmos web site). Best option is VMware, which provides a free VMPlayer.

Lecture Plan (2022)

Week 1: Introduction & Instruction Set Review & Chisel: Overview

Reading: H & P: Chapter 1, Appendix A, and RISC-V ISA document; Chisel: Chapter 1
Lab: FPGA Hello World with Chisel
Assignment: Instruction set comparison

Week 2: The JVM & Motivation & Chisel: Basic Operations

Reading: H & P: Chapter 1; Chisel: Chapter 2-3
Lab: UART in Chisel or lab2

Week 3: Pipeline Review (self study)

Reading: H & P: Appendix C;
Lab: Continue with Chisel examples

Week 4: Cache Review & Chisel: Scala and Chisel Background

Reading: H & P: Appendix B and Chapter 2; Chisel: Chapter 4-6
Lab: Continue with Chisel examples

Week 5: Time-Predictable Computer Architecture & Chisel: Customized Circuit Generation

Reading: Paper: Time-predictable Computer Architecture and T-CREST: Time-predictable Multi-Core Architecture for Embedded Systems; Chisel: Chapter 9
Lab: Patmos exercise

Week 6: Instruction Level Parallelism

Reading: H & P: Chapter 3 Section 3.1 till 3.3
Lab: Start of your project

Week 7: IO and Interconnect

Reading: Patmos handbook: Section 3.6 and 3.7
Lab: Present your project idea, project work

Week 8: Multicore Synchronization (Tórur Biskopstø Strøm)

Reading: H & P: Chapter 5.5
Lab: Project work

Week 9: Instruction-Level Parallelism II

Reading: H & P: Chapter 3
Lab: Project work

Week 10: Thread-Level Parallelism

Reading: H & P: Chapter 5
Lab: Project work

Week 11: Dynamic Reconfiguration in Multi-Core Real-Time Systems (Luca Pezzarossa)

Reading: TBD
Lab: Project work

Week 12: Chip-Multiprocessing