Proposed lecture plan

  lecture contents material

workload
in-class prepare
1 introduction Review on binary number systems: sign and magnitude, one's complement, two's complement, binary signed digit, floating point slides 2 2
2 adders RCA, FA inversion property, CLA, CLA tree, carry save, carry skip, bit-serial slides 6 6
3 multipliers array multiplier for positive and 2's complement numbers, Baugh Wooley, carry save adder array, Wallace tree, Booth encoding, bit-serial multipliers, case study, comparison with synthesis approach slides 6 6
4 dividers Dividers: restoring algorithms, sequential implementation, non-restoring algorithms, radix 4 SRT algorithm, implementation example slides 6 6
5 digital filters multirate filters, averaging, FIR, IIR, bit-serial implementations of decimation and interpolation filters, optimization techniques for bit-serial structures, clocking strategies, Matlab toolbox, design examples slides 12 12
6 SW-programmable DSP cores definition, comparison to microcontroller, data types, loops, addressing modes, instruction set, architecture comparison, VLIW architectures slides 6 6
7 asynchronous circuits while all previous chapters assume synchronous clocking, asynchronous design principles might prove to be an interesting alternative, a brief overview is given in this unit. slides 4 4
8 IP integration and platform based design the design flow for VLSI/SoC design is discussed in this lecture unit slides 4 4
9 lab 1 the design of an FIR filter will be carried out using functions of the Matlab toolbox - filter specifications will be assigned and all required toolbox functions are made available on the web - the VHDL code of the FIR filter needs to be developed and simulated with a suitable testbench - optionally the filter will be implemented on an FPGA or Standard Cell ASIC toolbox functions and manual, filter specifications 20 20
10 lab 2 a poly-phase filter will be designed using functions of the Matlab toolbox - filter specifications will be assigned and all required toolbox functions will be made available on the web - the filter is to be optimized in terms of hardware cost and power consumption and the results are to be compared to a single-phase implementation fulfilling the same specification toolbox functions and manual, toolbox functions 24 24